1. Field of the Invention
The present invention relates to floating-gate non-volatile memories, such as flash memories, and method of fabricating the same.
2. Description of the Related Art
As is known in the art, the NOR cell architecture is commonly used within floating-gate non-volatile memories. FIG. 1 illustrates a typical structure of an NOR flash memory, which is disclosed in Japanese Laid-Open Patent Applications No. H11-31800 and H11-145428. In this NOR flash memory, active regions 101 and isolation dielectrics 102 are alternately arranged in a memory array. Word lines 103, which function as control gates, are disposed to intersect the active regions 101 and the isolation dielectrics 102. The intersections of the active regions 101 and the word lines 103 are used as flash memory cells 110, with floating gates (not shown) provided therebetween. Drain regions of the flash memory cells 11 are formed within the active regions 101, and drain contacts 104 are connected to the drain regions. Source regions 105 are formed through a self-aligned source (SAS) technique so that the word lines 103 are positioned between the drain contacts 104 and the source regions 105. Source contacts 106 are connected to the source regions 104.
A drawback of the flash memory structure shown in FIG. 1 is irregularity in the in-plane structure near the source contacts 106. In the structure shown in FIG. 1, the respective intervals of the isolation dielectric 102, the floating gates, and the drain contacts 104 are not constant; the intervals of the isolation dielectric 102, the floating gates, and the drain contacts 104 near the source contacts 106 are different from those away from the source contacts 106. Additionally, the structure shown in FIG. 1 requires the word lines 103 to be curved near the source contacts 106 for providing room for the source contacts 106. Such irregularity enhances the proximity effect during the lithography process, and thereby undesirably causes dimension variances of the memory cells. The dimension variances of the memory cells may cause variances in the memory cell characteristics, and undesirably reduce the operation margin.
Japanese Laid-Open Patent Application No. H11-31800 (previously presented) discloses a flash memory structure for reducing the irregularity in the in-plane structure near the source contacts. In this structure, as shown in FIG. 2, active regions 201 and isolation dielectrics 202 are alternately arranged at constant intervals. Word lines 203, which functions as control gates, are disposed to intersect the active regions 201 and the isolation dielectrics 202. It should be noted that the word lines 203 are free from curvature. Drain contacts 204 and source contacts 205 are arranged in a direction parallel to the word lines 203. Source regions 206 are formed through an SAS technique to oppose the arrays of the drain contacts 204 and the source contacts 205 across the word lines 203. Memory cell transistors are disposed at the intersections of the active regions 201 and the word lines 203. Some of the memory cell transistors are used as depletion transistors 211, which is unable to store data, while the remainders of the memory cell transistors are used to actually store data therein. The depletion transistors 211 provide electrical connections between the source contacts 205 and the source regions 206. Such structure avoids the word lines 203 being curved, and thereby effectively improves regularity in the in-plane structure. The aforementioned Patent Application discloses two techniques for providing depletion transistors 211: one is selective implantation of n-type impurities into the channel regions of the relevant memory cell transistors, and the other is excessive erase of the relevant memory cell transistors.
A drawback of the structure shown in FIG. 2 is difficulty in the formation of the depletion transistors 211. The formation of the depletion transistors 211 through impurity implantation requires forming a resist pattern having openings to the channel regions of the depletion transistors 211. This is quite difficult as a matter of fact, because the active regions 201 are usually arranged at intervals of the minimum dimension of the design rule, and this makes it difficult to establish the alignment margin of the resist pattern.
The formation of the depletion transistors 211 through excessive erase, on the other hand, suffers from operation instability of the depletion transistors 211. During read operations and program operations of the memory cells 210, the word lines 203 are supplied with a positive bias, and this causes electron drift currents through the channel regions. The electrons relevant to the drift currents are partially injected into the floating gates (this phenomenon is known as soft write), and this leads to gradual increase in the threshold voltages of the depletion transistors 211. The increase in the threshold voltages eventually results in that the depletion transistors 211 not to work. As thus described, the use of the depletion transistors for avoiding the structure irregularity near the source contacts is not desirable from the easiness of manufacture.
Therefore, there is a need for providing a novel technique for improving regularity in the memory array structure within the floating-gate non-volatile memory.